Embodiments of the present invention relate to digital circuits, and more particularly, to an entry latch for interfacing static logic with dynamic logic.
Dynamic (or domino) logic circuits are often employed in high performance systems. For example, consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, microprocessor 102 comprises many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-chip cache 106. Microprocessor 102 may also communicate to other levels of cache, such as off-chip cache 108. Higher memory hierarchy levels, such as volatile system memory 110, are accessed via host bus 112 and chipset 114. In addition, other off-chip functional units, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with microprocessor 102 via appropriate busses or ports.
Some or all of the functional units making up a computer system as described above may comprise dynamic logic circuits. Entry latches are used to interface static logic with dynamic logic. A prior art entry latch at the circuit level is shown in FIG. 2. The clock signal is represented by xcfx86. Static input signals are provided at input ports 202 (there may be one or more input ports), which are connected to static logic (not shown). A dynamic output signal is provided at output port 204, which is connected to dynamic logic (not shown). nMOS pulldown network 218 comprises one or more nMOSFETs to perform a logical function on the static input signals, where input ports 202 are connected to various nMOSFET gates within nMOS pulldown network 218. The dynamic output signal is LOW during the pre-charge phase when clock signal xcfx86 is LOW, and the dynamic output signal is either LOW or HIGH during the evaluation phase when clock signal xcfx86 is HIGH, depending upon the logical function performed by nMOS pulldown network 218.
The behavioral operation of the entry latch in FIG. 2 is fairly straightforward, and accordingly only a brief description is provided. Keeper 210 comprises inverter 212, pullup pMOSFET 214, and pulldown nMOSFET 216. When clock signal xcfx86 is LOW during a pre-charge phase: pullup pMOSFET 206 is ON so that node 208 is HIGH; inverter 212 provides a LOW dynamic output signal at output port 204 so that pulldown nMOSFET 216 is OFF; and pullup pMOSFET 214 is ON. Static input signals at input ports 202 are setup before the rise of clock signal xcfx86. At the beginning of an evaluation phase when clock signal xcfx86 transitions from LOW to HIGH: pullup pMOSFET 206 switches OFF; nMOSFET 220 switches ON; but nMOSFET 222 will still be ON because of the signal delay introduced by inverter 224. With both nMOSFETs 220 and 222 ON at the beginning of an evaluation phase, a conditional low impedance path will be provided between node 208 and ground, depending upon the static input signals and logical function performed by nMOS pulldown network 218. If a low impedance path is provided between node 208 and ground, then nMOSFET 216 will switch ON and pMOSFET 214 will switch OFF, and node 208 is held LOW. But if no low impedance path is provided between node 208 and ground, then pMOSFET 214 will continue to stay ON and node 208 would be kept HIGH. After a signal delay introduced by inverter 224, nMOSFET 222 will switch OFF. In this way, a dynamic logic signal is latched at node 208, and consequently also at output port 204.
It is to be noted from the above description that at the beginning of an evaluation phase in which a low impedance path is provided between node 208 and ground, there is contention between nMOS pulldown network 218 and pullup pMOSFET 214. This contention contributes to gate delay and dynamic power consumption. Reducing the size of pullup pMOSFET 214 may reduce this inherent gate delay and dynamic power consumption, but at the expense of increasing the noise margin and soft error rate, which may be an unacceptable tradeoff. Consequently, there is utility in an entry latch with reduced gate delay and dynamic power consumption without the drawback of increased noise margin and soft error rate.